Reverse Dependencies of pyverilog

The following projects have a declared dependency on pyverilog:

• autobridge — AutoBridge
• magma-lang — An embedded DSL for constructing hardware circuits
• my-verilog — a verilog package based on python3
• ninety — A scalable pipeline for synthetic code SFT dataset generation
• pyipcore — (PyQt5 based) Create "Ipcore" from verilog(Need iverilog). Provide "Param Value" and "Port Control" function. This kind of IpCore is not safe, only for convenience
• tapa — Extending High-Level Synthesis for Task-Parallel Programs
• tlpc — High-level synthesis task-level parallelization