| Metadata-Version: |
2.1 |
| Name: |
pySVModel |
| Version: |
0.5.1 |
| Summary: |
An abstract SystemVerilog language model (incl. Verilog). |
| Author: |
Patrick Lehmann |
| Author-Email: |
Paebbels[at]gmail.com |
| Home-Page: |
https://GitHub.com/edaa-org/pySVModel |
| Project-Url: |
Documentation, https://edaa-org.GitHub.io/pySVModel |
| Project-Url: |
Source Code, https://GitHub.com/edaa-org/pySVModel |
| Project-Url: |
Issue Tracker, https://GitHub.com/edaa-org/pySVModel/issues |
| License: |
Apache-2.0 |
| Keywords: |
Python3 Verilog SystemVerilog Language Model Abstract |
| Classifier: |
Operating System :: OS Independent |
| Classifier: |
Intended Audience :: Developers |
| Classifier: |
Topic :: Utilities |
| Classifier: |
Topic :: Scientific/Engineering :: Electronic Design Automation (EDA) |
| Classifier: |
Topic :: Software Development :: Code Generators |
| Classifier: |
Topic :: Software Development :: Compilers |
| Classifier: |
License :: OSI Approved :: Apache Software License |
| Classifier: |
Programming Language :: Python :: 3 :: Only |
| Classifier: |
Programming Language :: Python :: 3.9 |
| Classifier: |
Programming Language :: Python :: 3.10 |
| Classifier: |
Programming Language :: Python :: 3.11 |
| Classifier: |
Programming Language :: Python :: 3.12 |
| Classifier: |
Programming Language :: Python :: 3.13 |
| Classifier: |
Development Status :: 3 - Alpha |
| Requires-Python: |
>=3.9 |
| Requires-Dist: |
pyTooling (~=8.0) |
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sphinx-copybutton (>=0.5.2); extra == "all" |
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| Provides-Extra: |
all |
| Provides-Extra: |
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| Provides-Extra: |
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| Description-Content-Type: |
text/markdown |
| License-File: |
LICENSE.md |