magia-hdl

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0.5.0 magia_hdl-0.5.0-py3-none-any.whl

Wheel Details

Project: magia-hdl
Version: 0.5.0
Filename: magia_hdl-0.5.0-py3-none-any.whl
Download: [link]
Size: 34291
MD5: d7fc60fcd6d7e5094f4845291c62e02c
SHA256: 0193aa571d1a7a7ed5d3dfb7da2c214b5e5a7f498b29fe0f7c856d11d9c9dc44
Uploaded: 2024-02-20 20:35:41 +0000

dist-info

METADATA

Metadata-Version: 2.1
Name: magia-hdl
Version: 0.5.0
Summary: Magia generates Synthesizable SystemVerilog in pythonic syntax
Author: khwong-c64
Author-Email: kin.hin.wong.c[at]gmail.com
Project-Url: Repository, https://github.com/magia-hdl/magia
License: LICENSE
Keywords: Verilog HDL,SystemVerilog,Synthesizable,RTL,HDL,Hardware Description Language,Code Generation,FPGA,ASIC,EDA,RTL Design
Classifier: Development Status :: 3 - Alpha
Classifier: License :: OSI Approved :: MIT License
Classifier: License :: Other/Proprietary License
Classifier: Programming Language :: Python
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Requires-Python: >=3.9,<4.0
Requires-Dist: hdlConvertor-binary (<2.4,>=2.3); extra == "full"
Provides-Extra: full
Description-Content-Type: text/markdown
[Description omitted; length: 4210 characters]

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